(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming field isolation.
(2) Description of Prior Art
The method of local oxidation of silicon(LOCOS) to form field oxide isolation around semiconductive devices built into the surface of silicon wafers has been practiced for over twenty-five years and has been adapted to many specific applications. In the process, a non-oxidizable mask of silicon nitride is formed over a thin layer of pad oxide grown on a blank silicon wafer. The mask is patterned by well known photolithographic methods and the wafer is oxidized, typically in steam, at temperatures in the neighborhood of 1,000.degree. C. The mask is patterned so that, after oxidation, mesa like regions of silicon are surrounded by a region of silicon oxide insulation. The semiconductive devices are then formed on the silicon mesas.
Over the years many problems with LOCOS have surfaced which have been addressed in a great variety of ways. Most notable are the problems which deal with the growth of oxide under the mask(birds beak) and the resultant uneven surface topology over the field oxide.
These problems still persist and become aggravated as the technology tends towards smaller, shallower devices at high densities. In addition new difficulties are encountered, for example, the field oxide thinning effect, which manifests itself when field oxide is grown by LOCOS in mask openings of less than about 0.5 to 0.6 microns. Many of these difficulties arise from the high stresses produced, not only by the growing oxide, but also by the nitride oxidation mask. High shearing stresses, caused by abrupt features in the silicon/silicon oxide profile, are produced in the silicon. These stresses lead to the formation of dislocations which propagate into the device active regions causing junction failure.
A promising replacement for LOCOS field oxide isolation has been found in trench isolation. Although deep trench isolation(DTI) has been used nearly as long as LOCOS for bipolar transistor isolation, it has not been widely practiced in the manufacture of MOSFET integrated circuits. More recently, however, as device densities increase and isolation widths become smaller, shallow trench isolation(STI) is gaining favor over LOCOS in MOSFET technology.
The Trenches are formed in the silicon around the semiconductor devices by reactive ion etching. They are then filled either entirely with silicon oxide or lined with silicon oxide and filled with another material such as polysilicon. Generally the trenches have vertical walls with high aspect ratios and thus it is difficult to provide sufficient dopant in the walls of the trenches to prevent channel formation which causes current leakage between adjacent MOSFET devices.
Furukawa, et. al., U.S. Pat. No. 5,643,822 forms trenches 0.1 to 10 microns deep and between 0.1 and 2 microns wide. Reactive ion etching(RIE) is used to form the trench using a mask with sidewall spacers. After the trench is formed, the spacers are removed and the base of the trench and a narrow region of silicon at the upper edge of the trench are implanted to form a channel stop.
Madan, U.S. Pat. Nos. 5,350,941 and 5,468,676 combines the use of LOCOS and trench isolation. The trenches are formed after a LOCOS oxidation process using anisotropic etching and a p-type dopant is then incorporated into the trench walls to form a channel stop. The dopant is either ion implanted or diffused from a deposited film source. Lur, U.S. Pat. No. 5,395,790 forms a recessed LOCOS isolation by first etching a trench in the silicon and then forming the LOCOS oxide.
Chiu, et.al, U.S. Pat. No. 5,401,998 forms trenches with sidewalls having an angle of 54.7 degrees with respect to the top surface of the wafer. Thereby a 0.degree. ion implantation is able to form a continuous channel stop along the entire surface of the trench. The trenches are formed by the anisotropic silicon etchant KOH on the &lt;100&gt; oriented silicon wafer. Narrow, high aspect ratio trench isolation required by current technology cannot be achieved by this method. Crotti, et.al., U.S. Pat. No. 5,068,202 forms trenches for field isolation using isotropic plasma etching with CF.sub.4 +O.sub.2. The etching is done using a pad oxide/silicon nitride/silicon oxide mask stack with sidewalls. The sidewalls function to reduce the design opening defined by the mask stack to compensate for the undercut produced by the isotropic plasma etch. The opening has a grossly rounded profile which permits implantation of a channel stop over the entire trench surface.
In another effort to form a uniform dopant concentration on the sidewalls and bottom of the trench for the purpose of providing reliable current channeling stop, Hosaka, U.S. Pat. No. 5,118,636 heavily dopes the entire trench region by ion implantation through the trench definition mask prior to opening the trench by RIE. The ion implantation is performed by a prescribed variation of implantation energy during the procedure to obtain the desired doping gradation within the trench region. Thereafter the trench is formed by reactive ion etching.
There are several problems associated with this procedure. One is that the directionality of the reactive ion etch is, to a large extent, not dependent on the doping profile and therefore there exists a high probability that the doping concentration at the base of the trench will be less than that along the sidewalls. The process window for the etch is therefore very narrow.
A second problem, which is also common to processes wherein RIE is used to form the trench, occurs when trench widths are scaled down to 0.25 microns and below. Here, RIE processing begins to fail with regards to vertical sidewalls due to polymer formation which tends to restrict penetration in deep trenches. FIG. 1 illustrates this point by showing a cross section a portion of a silicon wafer 10 with a trench opening 20 having a design width larger than about 0.25 microns and another trench opening 22 having a design width of less than 0.25 microns. The etch mask 11 comprises a pad oxide 12, a silicon nitride layer 14, and a photoresist layer 16. The mask 11 is initially formed by patterning the photoresist layer 16 using conventional photolithographic methods and then etching the opening in the pad oxide and silicon nitride layers by RIE procedures well known by those in the art.
When trenches in the silicon are etched by RIE, a polymer is formed along the silicon sidewall. The polymer protects the sidewalls from lateral etching. In the larger (&gt;0.25 micron) opening 20 the steady state polymer buildup on the sidewalls 19 is small compared to the width of the opening and therefore does not obstruct the vertical etching. In contrast, the steady state polymer buildup 18 in the smaller (&gt;0.25 micron) opening 22 is significant compared to the width of the opening and therefore tends to narrow and eventually close off the etching front, resulting in a tapered, undersized trench.
Other difficulties associated with isolation trenches formed by RIE include plasma damage, not so much at the base of the trench but in the upper portions where sensitive gate oxides are formed. RIE formed trenches generally have sharp corners which cause the formation of stress and crystal dislocations during subsequent oxidation. The dislocations propagate diagonally from the corners into junction areas resulting in junction leakage and shorts.